Radeon 9700 Pro

On August 7, 2002 ATI announced a new chip - ATI RADEON 9700 PRO. The main quality of the new chip is full hardware support for the requirements dictated by Microsoft's DirectX9 specifications.
Tellingly, the chip was announced long before the release of the final version of DirectX9. The new chip from ATI significantly outperformed other 3D gaming chips existing at that time, both in terms of complexity and technical characteristics, and while NVIDIA was figuring out the new technological process and preparing the NV30 release, it had every chance of becoming the sole leader in the world of game graphics .

Here are the key characteristics of the chip from ATI:
General information:
Manufacturing technology - 0.15 µm;
Number of transistors - ~110 million;
Package type - FCPGA;
Clock frequency - 325 MHz in ATI RADEON 9700 PRO version;
Memory bus - 256 bit DDR SDRAM;
The maximum amount of video memory - 256 MB;
Video memory clock rate - 620(310 DDR) MHz in ATI RADEON 9700 PRO version;
Support for AGP 2X (3.3v), 4X (1.5V), 8X (0.8v) and Universal AGP 3.0 (2X/4X/8X);
Support for PC2002 specifications.
3D part:
Eight pixel pipelines that meet the requirements of the DirectX 9 pixel shader specification version 2.0 (SMARTSHADER 2.0 technology from ATI);
One texture fetch unit per pixel processor;
Support for bilinear, trilinear, anisotropic and a combination of trilinear and anisotropic texture filtering;
Four vertex pipelines that meet the requirements of the DirectX 9 vertex shader specification version 2.0 (SMARTSHADER 2.0 technology from ATI);
Support for full-screen anti-aliasing by multisampling with 2, 4 and 6 subpixels (SMOOTHVISION 2.0 technology from ATI);
Support for polygon tessellation, continuous and adaptive tessellation, N-patches, displacement maps (TRUFORM 2.0 technology from ATI);
Support for memory bandwidth efficiency improvement technology (HyperZ III technology from ATI).
2D part:
Using pixel shaders for video processing (VIDEOSHADER technology from ATI);
MPEG4/DivX compression artifact filtering (ATI FULLSTREAM technology);
DVD hardware decompression, adaptive deinterlacing, motion compensation;
Image output in YPrPb component format;
Two CRT controllers;
Two built-in 400 MHz RAMDACs;
Built-in TMDS transceiver with a conversion frequency of 165 MHz;
Block diagram:

The characteristics of the new chip from ATI inspired respect - it was a real "monster": more than 100 million transistors, a clock frequency of 300 MHz, a 256-bit memory bus, 8 pixel and 4 vertex pipelines, DirectX9 compatibility.

Pixel pipelines.

First of all, it is striking that for the "cut down" RV250 it was the norm, but, it seems, could not be considered normal for a "high-end" class gaming accelerator - the ATI RADEON 9700 pixel pipelines had only one texture module each. However, such a construction of ATI R300 pixel pipelines is quite justified. The ATI RADEON 9700 had twice as many pixel pipelines as compared to video cards, which reduced the issue of insufficient texturing speed - the R300 eight-cylinder engine had enough horsepower to show itself worthy. -secondly, R300 texture modules were able to sample eight texture samples per clock - 4 samples each from two adjacent MIP levels, and perform trilinear filtering "free" in terms of chip cycle consumption.
Thirdly, the presence of two or more texture modules in the pixel pipeline would cause an increase in the amount of data read from textures per clock by a factor of two or more, and would require an increase in the volume of caches. Otherwise, even its 256-bit memory bus would not be enough for the R300 - in its current form, each of the R300 pixel pipelines, for example, when applying a 32-bit texture per clock, requested up to 256 bits of data (8 texture samples of 32 bits each), all eight pipelines in total - 2048 bits.

HyperZ III

In order to claim leadership among high-end gaming accelerators, having a high fill rate and a wide memory bus is not enough. It is necessary to efficiently use the resources of the graphics chip and the memory bus.
The ATI RADEON 9700 implemented ATI's proprietary technology, HyperZ III. The task of this technology is to avoid unnecessary processing of pixels that are obviously not subject to rendering, that is, those that are farther from the observer than those already drawn. For example, in the case when one of the polygons is partially or completely covered by another, then the part of the pixels of the far polygon, covered by the near polygon, can not be drawn. Thus, the graphics chip got rid of a significant amount of unnecessary work, at the same time, the efficiency of using the available video memory bandwidth also increased.

Hierarchical Z

Simplified implementation of a hierarchical Z-buffer.
The idea of ​​a hierarchical Z-buffer is quite simple: in addition to the Z-buffer itself, a pyramid of "low-resolution Z-buffers" is organized, organized like texture MIP levels.
Each of these new buffers is halved horizontally and vertically compared to the previous Z-buffer. In this case, each Z value from the lower resolution buffer must be written to the largest of the 4 corresponding Z values ​​of the previous higher resolution buffer.
ATI RADEON 9700 used a pyramid of three levels of Z-buffers - the usual Z-buffer, which serves as the base of this pyramid, and two more levels, having horizontal and vertical dimensions, reduced relative to the standard Z-buffer, respectively, by four and eight times :

Thus, while each value of the standard Z-buffer corresponds to one pixel in the image, the values ​​from the next levels of the pyramid store the largest Z-values ​​from areas containing, respectively, 4x4 and 8x8 pixels.

Fast Z Clear

Fast cleaning of the Z-buffer.
After building and displaying the image, the information contained in the Z-buffer is no longer relevant and must be erased. Simply put - between frames you need to reset the Z-buffer.
RADEON 9700, according to ATI, resets the Z-buffer, writing not individual values, but 8x8 blocks - 64 values ​​at once.
Such zeroing of the Z-buffer can be directly implemented, having a hierarchical Z-buffer in service. To initialize the entire pyramid of Z-buffers, it is enough to write the initial values ​​only to the Z-buffer of the lowest resolution - then, when building a frame, the pyramid of Z-buffers will automatically be kept up to date. Thus, by the way, the previously stated assumption that the "upper" Z-buffer of the low-resolution Z-buffers pyramid on the ATI RADEON 9700 corresponds indirectly to the 8x8 pixel blocks .

Z Compression

Compression of data read from the Z-buffer or written to the Z-buffer. The effect of lossless Z-buffer compression is the result of Hierarchical Z. In addition to discarding pixels that cannot be processed, Hierarchical Z effectively reduces the number of reads and writes of Z-buffer values, which make up a large proportion of the total data stream transmitted over memory bus.

New memory controller

The ATI RADEON 9700 has a memory controller "split" into 4 channels - this is familiar to us since the days of NVIDIA GeForce3:

In fact, in this case, the memory controller is 4 independent controllers with a bus width of 64 bits for each. In this case, the total width of the memory bus is 256 bits.

New Anisotropic Texture Filtering Algorithm

When developing the new chip, the ATI team of engineers took into account all the remarks made on the quality of anisotropic texture filtering on previous chips - the impossibility of combining it with trilinear texture filtering and poor performance of the algorithm on inclined surfaces.
The new anisotropic texture filtering algorithm, being an improved version of the old, "fast" algorithm from ATI, worked much better on inclined surfaces and, finally, allowed using a combination of trilinear and anisotropic filtering.

SMOOTHVISION 2.0

The new full-screen anti-aliasing technology, SMOOTHVISION 2.0, implemented in the ATI RADEON 9700 PRO, was one of the varieties of multisampling. Unlike SMOOTHVISION on ATI RADEON 8500, 9000 / PRO, supersampling with subpixels arranged on an ordered grid (Ordered Grid Super Sampling, OGSS), ATI RADEON 9700 PRO, when SMOOTHVISION 2.0 was enabled, calculated subpixels only at polygon boundaries, without performing additional unnecessary work for pixels located in the "insides" of triangles. That is, now, at last, the idea of ​​multisampling, which first appeared in NVIDIA GeForce3, has turned out to be implemented in the ATI chip.

VIDEOSHADER

The possibility of using pixel shaders for processing video streams was named VIDEOSHADER by ATI.
Thanks to VIDEOSHADER support, ATI RADEON 9700 got rid of (which means it becomes a bit simpler, more reliable and cheaper) some blocks designed specifically for working with video, and instead used pixel shaders.

HYDRAVISION

This word has been familiar to us since the appearance of ATI RADEON VE. Technology HYDRAVISION ATI calls support for multi-monitor configurations.
In this regard, ATI RADEON 9700 did not have any revolutionary changes - like previous chips, R300 supported image output to two analog monitors, one analog + one digital, analog monitor + TV, digital monitor + TV.

Pixel shaders

Pixel shaders DirectX9 version 2.0 have become much more complex. The new specifications dictated the following hardware requirements:
Use of data from 16 textures during shader execution;
32 addressing operations;
64 arithmetic operations;
16 general purpose registers;
16 registers for storing constants.

ATI RADEON 9700, as it should be for a DirectX9-compatible accelerator, fully complied with these requirements.
For comparison - specifications of pixel shaders version 1.4, whose hardware support is implemented in ATI RADEON 8500, 9000/PRO (R200, RV250):
Use of data from 6 textures during shader execution;
2*6 addressing operations;
2*8 arithmetic operations;
6 general purpose registers;
8 registers for storing constants

ATI RADEON 9700 vertex pipelines, vertex shaders version 2.0

The vertex shaders of the new version also differ significantly from the 1.1 vertex shader specification. Command flow control:
Programs executed by vertex pipelines of a Direct9-compatible accelerator - vertex shaders - have become even closer to the usual understanding of programs: they now have the ability to control the command flow: loops, conditional and unconditional jumps, subroutine calls.

More instructions, more registers:
In the new vertex shader specification, the program length has increased from 128 to 256 instructions, the number of general purpose registers from 8 to 16, the number of registers for storing constants from 96 to 256.

While NVIDIA GeForce4 Ti and ATI RADEON 8500 each have two vertex shaders, ATI's new chip has four vertex processors working in parallel.

At the time of its release, the ATI RADEON 9700 PRO became the highest-performance gaming chip that existed at that time. Tellingly, the performance of the ATI RADEON 9700 PRO was so high that it was not the video card that often became the "weak spot" in the system, but the processor.

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