The latest PCI Express 7.0 standard: An up-to-date update.

In the latest news from the world of data centers and high performance computing, the PCI Special Interest Group (PCI-SIG) holds its annual developer conference.

Bringing together developers and ecosystems from the main expansion bus industry, the event offers many technical sessions for hardware professionals. However, for the public, the key point is usually the annual update from the SIG on the state of the ecosystem.

Things haven't changed this year, with a fresh update on PCIe 7.0 development status and PCIe 6.0 cabling acceptance and efforts in the spotlight.

The PCI Express 6.0 standard was approved last year, and PCI-SIG quickly moved on to work on the next generation of PCIe, 7.0, announced at last year's developer conference. The goal of PCIe 7.0 is to double the throughput of PCIe devices, increasing single-path throughput to 16GB/s in both directions, and the popular x16 slot to 256GB/s in each direction.

PCI-SIG has completed the first version of the draft specification, version 0.3, and is ready to distribute it to group members. This marks an important step in the development of the standard.

PCIe 7.0 retains PAM4+FLIT encoding like its predecessor. Therefore, the next standard will mainly save on the development of its logic level.

The development of the PCIe 7.0 standard is expected to be completed in 2025, following the three-year development cycle of the PCI-SIG standards.